Firmware Architect

At Kandou, we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable adoption. Our proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient.

Unlike traditional interconnects, our solution reduces power consumption significantly while preserving high bandwidth and ultra-low latency — unlocking unprecedented efficiency for AI training and inference at scale. Kandou’s architecture is not just an incremental improvement — it’s a foundational shift in how AI hardware is built for the future. We are actively seeking a Firmware Architect based in India (Hyderabad or Bangalore).

Define firmware architecture for 224G/lane AEC retimer (boot, config, calibration, link training, equalization, FEC, telemetry) Implement link training for IEEE 802.3ck (100G/lane) and 802.3dj (200G/lane), including adaptation algorithms and fallbacks Own FEC interaction (KP4, RS-544) and telemetry pipeline for Predictive Telemetry Lead silicon bring-up, partnering with ASIC design and signal integrity Ensure standards compliance (IEEE 802.3ck/dj, OIF-CEI, CMIS, OSFP) Partition HW-fixed vs. FW-adaptation (equalization, SNR monitoring) Travel: Up to 15% (silicon bring-up, standards meetings) Skills: Good knowledge of C (C99, MISRA), assembly for critical paths, Python for t