Team Credo is seeking a Sr. Staff Design Engineer to drive both hands-on digital ASIC design and strategic architecture direction for our High-Performance Network Interface IP portfolio. This role has direct impact on the interconnect infrastructure enabling next-generation AI and HPC systems.
Depending on the candidate's strengths, the focus may span from leading RTL development and design execution to shaping product roadmaps, architecture requirements, and long-range technology investments.
The ideal candidate brings deep expertise in computing and communication systems -including memory subsystems, inter- and intra-chip interconnects, Ethernet, CXL, PCIe, UCIe, and UALink - and understands how these technologies support scalable AI infrastructure across accelerator, chiplet, and data center environments.
Base salary range is $144,000 - $228,000 a year. The base salary offer will depend on factors such as education, experience, training, skills, qualifications, and location. This position is also eligible for a discretionary bonus, equity and a full range of medical and other benefits.