Design-for-Test (DFT) Engineer - ASIC Backend - (Associate, Experienced, or Lead)
- Experience
- 9+ years
- Education
- Master's degree
- To apply
- cover letter
Job Description At Boeing, we innovate and collaborate to make the world a better place. We're committed to fostering an environment for every teammate that's welcoming, respectful and inclusive, with great opportunity for professional growth. Find your future with us.
Boeing Space, Intelligence & Weapons Systems has an exciting opportunity for multiple Design-for-Test (DFT) Engineers - ASIC Backend to join us as part of our Boeing Electronic Products team at the heart of Boeing's products to support advanced digital subsystem development in an aerospace environment in El Segundo , CA . Position overview The DFT team drives architecture, verification, and post-silicon validation for leading-edge ASICs. We seek engineers across experience levels (Jr → Principal) to design and validate test access mechanisms, memory BIST, scan compression, and related test infrastructure.
Design and implement DFT architectures: TAP/JTAG, IJTAG (IEEE 1687), Boundary Scan (BSCAN), MBIST, and scan compression Develop and validate TAP/JTAG and IJTAG infrastructures, BSDL/ICL/PDL artifacts, and ATPG pattern generation Drive pattern generation, coverage optimization, memory test validation, and silicon debug (scan, at-speed, bring-up) Integrate DFT features across the chip design flow and collaborate with cross-functional teams to ensure robust DFT integration Coordinate with external partners/customers on custom DFT interfaces and security requirements when applicable Contribute