Physical Design Engineer

AI Vision Processors For Edge Applications Our solutions make cameras smarter by extracting valuable data from high-resolution video streams. Job Description The Physical Design Engineer will be an integral part of the physical design team with all aspects of physical design implementation and verification tasks for Ambarella’s cutting edge low power AI SoC from Netlist to GDSII. The Physical Design Engineer will be responsible for the following areas throughout all phase of SoC implementation process; floor-planning, auto place and route, static timing analysis, eco implementation, signal integrity analysis, EM/IR analysis, formal verification, and physical layout verification (LVS/DRC/DFM) at block and/or full chip level.

BS/MS in EE/computer science or equivalent experience 3- 5+ years’ experience, Good understanding in VLSI digital design/Layout/Timing closure Basic knowledge on circuit design, device delays, and timing at gate-level Familiar with industry EDA tools such as Cadence Innovus/Quantus/Tempus, Synopsys Fusion Compiler/ICC2/StarRC/Primetime and Mentor Calibre. Proficient programming and scripting skills (Perl, Python, TCL, C-shell, make) Hardware Design Languages like Verilog, VHDL Self-motivated team worker, good verbal and written interpersonal skills. Experience with Cadence Innovus/Genus/Conformal and Synopsys Primetime/StarRC would be an added advantage.

Solid understanding of hierarchical physical design strategies, methodologies and nanomete