Descrizione
Bachelor’s or Master’s degree in Electrical Engineering or Electronic Engineering. Proven experience in SoC design verification, including unit and combine test strategies. Strong knowledge of AMBA protocols: AHB, APB, AXI (mandatory) and IPs Proficiency in verification methodologies such as SystemVerilog, UVM (preferred), and SVA.
Familiarity with programming languages like Verilog, assembly, C/C++. Proven ability to communicate clearly and transparently with both internal teams and global customers. Capable of managing daily workflows and leading a design team with full ownership and accountability.
Nice to have
Basic understanding of formal verification techniques and scripting using TCL, Python.
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