Senior ASIC DFT DV Engineer (Hybrid)

The application window is expected to close on: 11/12/2026 This is a hybrid role with three days per week at Cisco’s San Jose location Meet the Team The Silicon One team creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow.

Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world. Your Impact ​ Responsible for thorough test planning and development of test benches to verify comprehensive Design-for-Test (DFT) architecture that supports ATE screening, in-system test, debug and diagnostics needs of the design Own the MBIST methodology across the Silicon One portfolio, driving unified, high-quality standards for memory testing.

Architect reusable, hierarchical infrastructures that scale across massive designs to accelerate time-to-market for future silicon. Work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive high-quality DFT verification. Minimum

​ Bachelor’s in Electrical Engineering or equivalent with at least 7+ years (or Master's with