Static Timing Analysis Design Engineer / Physical Design

We are seeking an experienced engineer for SoC Static Timing Analysis for advanced semiconductor products. This role will own end-to-end Timing Constraints and Static Timing Analysis across complex designs, driving initial constraints development and timing correlation in early stages to final Timing Signoff for cutting-edge technology nodes. This role would work with implementation engineers from synthesis through final timing closure to close timing, including timing correlation, debugging failing timing paths, providing timing ECOs (automated and manual).

The ideal candidate demonstrates technical timing and constraints expertise to close timing on a given design on silicon along with capability of using timing analysis tools to correlate timing and generate automate as well as manual timing fixes. Key

• End-to-End Constraints and Timing Signoff Ownership Drive Timing Constraints Creation and Validation Work with Frontend, IP and DFT teams to Validate Constraints, Resolve timing issues Work hand-in-hand with Implementation owner(s) and Full Chip STA team to close Timing Timing Correlation and Timing Path Debug from synthesis through timing signoff Provide timing feedback during all design stages Create Automated and Manual timing fixes for implementation 2. Team Leadership & Organization Development Participate career development. Interface with Implementation owner(s) and Full Chip STA team. 3. Technical Strategy & Innovation Provide feedback to improve