Descrizione
About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow.
For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The Central Engineering ASIC Design Services Team within Marvell provides chip solutions for next generation 5G carriers, cloud data centers, enterprise, and automotive applications. As a manager within the ASIC team, you will have the opportunity to lead an experienced team and growing team of physical design, static timing analysis (STA).
You will also have the opportunity to interact with customers and the worldwide team to develop solutions to meet our customer’s needs. What You Can Expect As a key member of central physical design team, you will provide backend design service for multiple Marvell SOC design groups, from floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff to physical verification (DRC/LVS/Antenna). You will have the opportunity to work on many varieties of challenging designs, i.e.
low power and high speed SOCs. You wi
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