Verification Engineer Platforms Team

• *Please note this role is only open to candidates currently located in and with working rights in the UK**

Location: Preferably based at one of our UK design centres (Bristol or Cambridge).

Welcome to […]

At […], we’re redefining the future of computing. Following a bold strategic pivot toward cyber-resilient semiconductor architectures, we are building next-generation processors and systems where security is embedded at the very core by design, not as an afterthought. As we expand our portfolio of secure, CHERI-enabled technologies and focus on delivering architecture-first security solutions, there has never been a more exciting time to join.

We are embarking on clean-sheet designs and expanding the teams of engineers who can establish high-quality working practices as they explore new ground. Be part of a global team shaping the next era of secure computing where innovation, ownership, and impact go hand in hand.

The impact you’ll make

Verification Strategy & Planning: Define comprehensive verification strategies, plans, test scenarios, and coverage goals from architectural specs, reviewing technical requirements from a verification perspective.

Testbench & Environment Architecture: Develop and maintain scalable, reusable IP- and system-level verification environments using industry-standard SystemVerilog/UVM, including stimulus generators, checkers, and formal verification setups.

Execution, Debugging & Closure: Run