PCIe Characterization Engineer | On-site Opportunity | Palo Alto, CA | Fastwater Staffing

Stack

Szczegóły

Bezpłatnie, po zalogowaniu.

Aplikuj

Prześlij CV — pracodawcy i rekruterzy z różnych krajów, którzy szukają takiego profilu, będą mogli napisać do Ciebie bezpośrednio.

Opis

📍 Location: Palo Alto, CA 📄 Employment Type: Contract 🏢 Work Arrangement: On-site 🚀 Start Date: TBD 💰 Compensation TBD — based on skills and experience Important Screening Requirements 5+ years of experience in post-silicon characterization, high-speed I/O (HSIO) validation, or memory electrical validation. Hands-on experience characterizing high-speed SerDes PHYs , particularly PCIe. Experience measuring eye diagrams, jitter, bit error rate (BER), and S-parameters . Proficiency with high-speed oscilloscopes, bit error rate testers (BERT), and VNA/TDR equipment. Ability to read and interpret schematics and PCB layouts. Experience debugging electrical issues directly at the probe point. Python scripting experience for laboratory test automation. Background in semiconductor, silicon, or systems companies, including SoC, GPU, networking, storage, or automotive compute. Must be willing to work on-site in Palo Alto, CA . About the Role We are seeking a hands-on PCIe Characterization Engineer to perform post-silicon electrical characterization and validation of high-speed SerDes physical-layer interfaces in a laboratory environment. The role focuses on conducting high-speed electrical measurements, analyzing signal integrity, and validating silicon performance. You will independently operate laboratory equipment, troubleshoot signal-level issues, interpret hardware schematics and PCB layouts, and automate characterization workflows using Python. The successful candidate will have

Pełny opis, firma i link do aplikacji — po zalogowaniu. Zaloguj się

Kontakty pracodawcy (e-mail/telefon/Telegram) są ukryte w publicznym podglądzie. Wyślij CV — a pracodawcy będą mogli napisać do Ciebie sami.