Design Verification Engineer, New Grad

Nova is a leader in next-generation AI infrastructure, delivering a full-stack inference platform for customers worldwide. At the core of Samba

Nova's technology is the RDU (Reconfigurable Dataflow Unit) — a chip built on a dataflow architecture rather than the traditional GPU model. Its decode performance is especially strong for agentic workloads like multi-turn agents, code generation, and long-running applications. RDUs are packaged into Samba

Rack, rack-scale hardware that lets customers deploy state-of-the-art models with better performance, greater energy efficiency, and faster time to value. About the Team The Design Verification team verifies the RDU, Samba

Nova's chip for AI workloads. We build System

Verilog and UVM environments for chip-level control and initialization, including sequencing, state transitions, clocking, and recovery, and work with architects, RTL designers, and firmware engineers. About the Role As a new grad Design Verification Engineer, you'll write testbenches, tests, checkers, and coverage in System

Verilog and UVM for RDU features. You'll run regressions, debug simulation failures, and work with RTL designers to find and fix bugs before tape-out.

Write and execute verification plans for chip-level control and initialization features Build System

Verilog and UVM testbench components, including sequences, checkers, assertions, and functional coverage Write directed and constrained-random tests to find corner cases Debug simulati