Physical Verification Engineer

Salience Labs is building an industry-defining approach to optical circuit switching for AI infrastructure, engineered for real latency reduction and cost savings. We're moving towards real-world deployment, and joining at this stage means genuine ownership over that next chapter, working alongside a highly technical team on one of the most consequential problems in AI infrastructure today.

We’re looking for a Physical Verification Engineer to drive DRC/LVS signoff for our integrated circuit and photonic integrated circuit (PIC) designs. You’ll work at the intersection of electronic and photonic design, running and debugging verification flows against foundry PDKs and helping keep our tapeouts clean.

Run and debug physical verification (DRC, LVS, extraction) on IC and photonic IC layouts

Debug LVS/DRC discrepancies, including port mismatches, hierarchy mismatches, and device recognition issues

Read, manipulate, and QA GDS/OASIS layout data

Maintain and extend verification runsets and rule decks

Build Python/Tcl/shell tooling to automate verification flows and triage error reports

Maintain verification libraries and runsets under version control, with controlled release processes

Handle third-party and foundry IP with care, following licensing terms

Work with design, layout, and CAD teams to close out verification issues ahead of tapeout

Document known issues, workarounds, and runset changes

3+ years of