ASIC Engineering Intern, Formal Verification

Meta is seeking an ASIC Engineer Intern, Formal Verification to join our Infrastructure Silicon organization. Our servers and data centers are the foundation upon which our rapidly scaling infrastructure efficiently operates and upon which our innovative services are delivered. In this role, you will be an integral member of an ASIC team building accelerators for some of our top workloads, enabling our data centers to scale efficiently.

You will have an opportunity to apply formal verification tools and methodologies to advanced IPs and sub-systems. Working alongside experienced ASIC engineers, you will contribute to formal verification planning, assertion development, formal testbench development and proof analysis on a scoped project of your own. You will learn to translate design intent into properties, analyze counterexamples and help establish the correctness of hardware designs.

Come work and learn alongside our expert ASIC engineers to build "Green" data center accelerators. Internships are twelve (12) to sixteen (16) weeks long Develop an understanding of the architecture, microarchitecture and intended behavior of the designs under verification.

Contribute to formal verification plans by identifying design requirements, properties to prove and scenarios to cover.

Verilog Assertions (SVA), assumptions and cover properties to verify design functionality, protocol behavior and corner cases.

Develop formal testbenches and harnesses, including clock, reset and