Lead Engineer - CAD Physical Verification

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets.

Learn more at [link] . Meet the Team As part of central CAD group, CAD Physical Verification (PV) team is responsible for supporting design and layout teams during chip development by debugging PV related queries, developing and supporting various PV decks like DRC, Antenna, Dummy fill, LVS and extraction.

In addition, the team collaborates and collects specs from other teams to code decks like PERC, Float, Density, XOR from scratch. The team is also responsible for developing and automating various flows and methodologies to improve verification quality and optimize performance.

Support design and layout teams to resolve any PV related issues during design development cycle Development and QA of various physical verification rule decks like DRC, Dummy fill, Antenna and other custom decks Conduct and drive impact analysis meetings with stakeholders for deck updates Collaborate closely with CAD, ESD