ASIC Engineer, Physical Design CAD

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Beschreibung

Meta's silicon engineering team is building custom infrastructure silicon to power the compute demands of AI, data center, and next-generation hardware platforms. The Infra Silicon Implementation CAD team owns the physical design flows and automation that take our designs from RTL handoff through synthesis, place and route, timing closure, and physical signoff. As a Physical Design CAD engineer, you will be responsible for building and owning the flow infrastructure used daily by PD engineers across concurrent tapeout programs. This is a high-leverage role: the automation you build directly determines how quickly a chip organization converges. Develop, maintain, and own stages of the digital physical design flow — synthesis, floorplanning and design planning, placement, CTS, routing, extraction, timing ECO, and STA signoff Build and extend flow automation in Python and Tcl, integrated with Meta’s internal build, job-scheduling, and continuous integration infrastructure Partner with PD engineers and design leads to debug flow and Quality of Release (QoR) issues on active tapeout programs, and convert recurring workarounds into supported flow features Qualify and integrate commercial EDA tools, drive issues to resolution with vendor application-engineering teams, and manage tool version migrations across programs Build constraint and netlist validation capability so design-intent errors are caught in-flow rather than at sign-off Develop QoR tracking, metrics, and dashboards tha

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