Senior Principal Design Verification Engineer
- Erfahrung
- ab 12 Jahren
- Ausbildung
- Master
We are seeking an experienced Senior Principal Design Verification Engineer to lead verification of complex SoC, IP, and modem subsystem designs. This role requires deep technical expertise, strong leadership, and the ability to influence architecture, methodology, and verification strategy across global engineering organizations.
- Own verification strategy, planning, execution, and signoff for complex SoC/IP and modem programs. • Architect scalable and reusable System
Verilog/UVM verification environments. • Develop verification plans, coverage models, assertions, scoreboards, and checking methodologies. • Drive coverage closure and verification signoff using data-driven quality metrics.
• Debug complex design and verification issues and drive root-cause resolution across teams. • Collaborate closely with architecture, design, firmware, validation, and software teams. • Lead technical reviews and influence microarchitecture and design decisions.
• Mentor verification engineers and help drive organizational verification excellence. • Coordinate effectively across global sites, time zones, and disciplines to ensure successful project execution. • Drive methodology, automation, and productivity improvements across projects.
• Travel domestically and internationally as required to support program execution and collaboration with global teams (approximately 5%). Required
- Bachelor's or Master's degree in Electrical Engineering, Electronics, Comput