Senior ASIC Design Engineer - DSP/Analog/SerDes

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Описание

Senior ASIC Design Engineer Celero Communications is an exciting and fast-growing semiconductor startup developing innovative technologies that power next-generation AI and data center infrastructure. Our products enable high-performance optical connectivity and next-generation optical transceivers and modems. Celero is seeking a highly skilled and motivated ASIC Design Engineer to join our team and contribute to the development of advanced ASICs for high-speed optical communication systems. The ideal candidate will have strong digital ASIC design expertise combined with hands-on experience in DSP, Analog, and/or SerDes technologies. Duties & Responsibilities • Design and implement high-performance digital circuits and ASIC blocks using Verilog and SystemVerilog. • Develop and integrate DSP, digital communication, and high-speed SerDes functionality into complex ASIC designs. • Work closely with Analog, SerDes, DSP, Architecture, Verification, Physical Design, and Systems teams to develop and integrate mixed-signal ASICs. • Participate in the design and development of high-speed data paths, signal processing blocks, control logic, and interfaces for optical communication systems. • Perform synthesis, timing analysis, lint, formal equivalence, Clock Domain Crossing (CDC), and related ASIC implementation and signoff activities. • Optimize designs for performance, power, and area (PPA). • Perform RTL simulation and debugging to ensure design functionality and performance. • Con

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