Physical Design and Verification Engineer

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Description

About Neuralink: We are creating devices that enable a bi-directional interface with the brain. These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world. Team Description: The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-machine interface applications. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future. Job Responsibilities and Description: The Physical Design and Verification Engineer will be responsible for RTL to GDSII Physical Design Implementation, including Synthesis, Placement, Clock Tree Synthesis, Detailed Routing and Optimization, in addition to Physical Signoff Verification. Required ) degree in Electrical Engineering and/or Computer Science or a related field, or equivalent experience. Minimum 5 years of experience in digital physical design and verification. Excellence in complete RTL to GDSII flow with strong experience in the usage of industry-standard Electronic Design Automation (EDA) tools for both physical design and timing signoff. Deep knowledge on industry standards and practices in physical design including physically-aware synthesis flow, floor-planning, and place & route, metal fill, chip finishing, signal integrity checks, and dynamic EMIR-Drop analysis, and formal ESD verifica

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