Senior Digital Verification Engineer

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Description

The Allegro team is united by a clear purpose—advancing technologies that make the world safer, more efficient, and more sustainable. With over 30 years of experience in semiconductor innovation, we bring that purpose to life across every part of the business—from breakthrough product development and customer success to how we show up for each other and the communities we serve. About the Role Allegro MicroSystems is seeking a Digital Verification Engineer to join our team developing next-generation magnetic position/current sensors, motor drivers, and power management ICs. You will be responsible for verifying complex digital and mixed-signal designs, ensuring first-pass silicon success for products that drive e-mobility, clean energy, automation, and robotics forward. Key Responsibilities Develop and execute verification plans for digital and mixed-signal IP and full-chip designs. Build and maintain constrained-random, coverage-driven testbenches using SystemVerilog and UVM. Define functional coverage, assertions (SVA), and checkers to measure and close verification goals. Perform block-level, subsystem, and top-level (full-chip) verification, including analog/digital interaction using Verilog-AMS / real-number modeling. Debug failures in collaboration with RTL designers, analog designers, and firmware teams. Contribute to regression setup, automation, and continuous-integration verification flows. Track and report coverage closure, bug metrics, and sign-off readiness. Part

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