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DFT Lead Engineer

LeadUSA-CA San Jose Innovation Drive, US1w ago
Market insights
📊 QA / Testing: salaries and demand on the market
Stack
serde
Details
Experience
12+ years
Education
Master's degree
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Description

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2.

If you already have a Candidate Account, please Sign-In before you apply. Job Description: Principal DFT Engineer […]'s ASIC Product Division is seeking candidates for a DFT position at our San Jose, California, Development Center. The successful candidate will be responsible for leading DFT programs all the way from chip level DFT specification, through to implementation and verification culminating in successfully releasing products to production.

The candidate would be required to work on various phases of SoC DFT related activities for […] APD (ASIC Products Division)’s designs – DFT Architecture, Test insertion and verification, Pattern generation, Coverage improvement, Post silicon debug and yield improvement to meet the product test metrics. It involves working with the Physical Design & STA team for DFT mode timing closure.

The role

could also involve direct interaction with external customers. It is expected that you can code using TCL, PERL, RUBY, PYTHON, C++ or similar.

Responsibilities

Understanding […] & customer DFT feature requirements & DPPM goals & defining appropriate DFT specifications for the ASIC Implementing DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration Working closely with STA and DI Engineers design closure for test Generating, Verifying & Debugging Te

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