Static Timing Analysis Engineer

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Description

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at [link] . Static Timing Analysis Engineer Austin, TX This position involves the development of timing constraints and timing closure signoff of low power Wireless SoCs and IP systems. These SoC devices are multi-core, multi-threaded processor subsystems with multi-level cache, capable of supporting multiple wireless protocols and application functionality, such as sensor hub, AI /ML and are specified to exceed best-in-class power targets. These SoCs deploy a complex, deeply gated clock network with many asynchronous clock sources. Responsibilities Develop timing constraints at both the IP and SoC level in collaboration with the designers Improve or evolve existing static timing analysis flows and methodologies. Develop required timing signoff criteria, such as aging, on chip variation, and signal integrity Analyze timing reports using scripting techniques to develop insights and drive rapid timing clo

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